There are many computationally intensive problems in the area of digital design and logic synthesis. Some of these have no “good” solution; that is, simply by their definition they have exponential run-times. In order to overcome this, we examine the possibility of a configurable hardware solution to speed up one such problem. The computation of the problem is carried out on a Field Programmable Gate Array (FPGA), where the problem is encoded in such a way that within certain parameters, the design of the solution need not be changed for working with a variety of benchmark circuits. This saves considerably on compilation and configuration times. The use of configurable hardware, however, still allows for reconfiguration in situations where the parameters change significantly enough to require an altered approach. We examine two implementations of the problem, which in this case consists of computing the autocorrelation coefficients for a Boolean function.

Type

Publication

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

Date

February, 2005

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